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Espressif Systems /ESP32-S2 /GPIO /STATUS_W1TC

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Interpret as STATUS_W1TC

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0STATUS_W1TC

Description

GPIO0 ~ 31 interrupt status bit clear register

Fields

STATUS_W1TC

GPIO0 ~ 31 interrupt status clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_STATUS_INTERRUPT will be cleared. Recommended operation: use this register to clear GPIO_STATUS_INTERRUPT.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data